1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a metal oxide semiconductor (MOS) transistor and a method of manufacturing the same.
2. Description of the Related Art
Fully depleted silicon-on-insulator (FD-SOI) technology has been widely used to create high speed, low power logic circuits. Using FD-SOI technology reduces parasitic capacitances associated with source, drain, and channel regions of semiconductor circuits, thereby allowing the circuits to operate at higher speeds. In addition, FD-SOI technology reduces the amount of leakage current occurring at source and drain junctions of the circuits, thereby lowering associated power consumption. Furthermore, shallow source/drain regions are readily implemented using FD-SOI technology, thus allowing the short channel effect to be readily constrained and thereby improving the scalability of the circuits.
Unfortunately, however, a substrate floating effect may occur in MOS transistors formed on an SOI substrate where an element in a channel region assumes a floating state electric potential. Furthermore, where a buried oxide layer (BOX) is formed below a silicon substrate, a self-heating problem often occurs in devices formed on the silicon layer. As a result, the range of applications where SOI technology can be used is restricted by the kinds of circuits to be formed.
As complementary metal-oxide semiconductor (CMOS) technology has continued to shrink in size, a variety of attempts to improve the performance of transistors with short channel lengths have been made. Among these attempts, a mechanical stress engineering technique has been proposed. According to the mechanical stress engineering technique, a local stress is applied to a channel region so as to control the carrier (electron or hole) mobility (μ) within a semiconductor material. Where the carrier mobility increases, the switching characteristics of the device are improved, thus enabling the manufacture of higher-speed devices.
Unfortunately, it is difficult to apply local stress to SOI devices because the silicon layer formed on the buried oxide layer (BOX) is too thin. In addition, cost poses an obstacle to the manufacture of devices using SOI technology because SOI wafers are extremely expensive.